Combination Lock Analysis Using VHSIC Hardware Description Language (Coursework Sample)
Designing a combinational lock for the unlock sequencesource..
Module name: Digital Control Design and Implementation.
Module code: EAC4022-N
In Course Assessment
Student name: Korir Lewis
Student ID: A0143510
Design of a Combinational lock state machine using VHDL.
(School of Computing, Engineering and Digital Technologies, Teesside University)
Contents TOC \o "1-3" \h \z \u Abstract PAGEREF _Toc69976112 \h 1Introduction PAGEREF _Toc69976113 \h 1Design of the state machine. PAGEREF _Toc69976114 \h 4Discussion PAGEREF _Toc69976115 \h 12Conclusion PAGEREF _Toc69976116 \h 12References PAGEREF _Toc69976117 \h 13
This paper presents the modelling of a “combination lock” state machine that activates an “unlock” output when a certain binary sequence is received. A combinational lock is a lock that is specific only to a set of symbols to dislodge and open. These symbols used to formulate a sequence are typically numerical, alphabetical, or even alphanumerical depending on the design preference. The combinational lock design is achieved using a state machine. A state machine generally refers to a machine that tracks internal states. State machines use a series of flip flops as memory to keep track of the state of the system. Mostly this combination of flip flops is connected to a common clock hence their name clocked synchronous state machine or rather to a common reset system that will reset all the flip flops simultaneously. There are two types of state machines: Mealy and Moore state machine. From the word description for the design the ‘combination lock’ machine is a Mealy machine. This paper proposes the use of VHDL (VHSIC Hardware Description Language) language for the design of the Mealy machine.
VHDL (VHSIC Hardware Description Language) is a general-purpose hardware description language that allows for the modelling and simulation of digital circuits before synthesis tools translate the design to real hardware (Synoria, 2011). VHDL has since become an IEEE standard and is widely used for industrial purposes. VHDL leads to naturally a top-down design methodology where the system is first specified at a high level and tested using a simulator. After which debugging can be done and the design can be refined leading to a structural description closely related to actual hardware desired.
The primary building blocks of a VHDL used to describe typical circuits include the header, the entity and the architecture body. The header is describes the logic libraries and declares the multilevel logic system that indicates the data types that are acceptable for the code. The Entity is a list of specifications of all input and output pins of the circuit while the architecture specifies how the circuit works (Ashenden and Kaufmann, 2010).
The most common way of modelling sequential logic in VHDL is the use of process. The general form of a process is as follows:
Process ( sensitivity_list)
The sensitivity list consists of signals that affect the sequential statements so that if any of the signal changes, the sequential statements are executed in sequence one time.
A Finite State Machine (FSM) is an abstract way of representing a sequential circuit and can be broadly classified into one of two types of machines, namely Moore or Mealy. According to Wakerly (1999), a Moore machine is an FSM such that the output depends solely on the state of the machine, whereas a Mealy machine is an FSM such that the output depends not only on the state but also the input.
For the design proposed above, since the network output depends on changes in the clock or the input X, then two signals should be on the sensitivity list. The network checks for the input X and matches it with the required sequence, that is, change of state depends on the input X. Also, the state register dictates that for every rising edge of the clock, the state is always updated to the next state. This requirement shifts the attention to a commonly used sequential statement, the if statement which is a Boolean expression evaluating if a statement is TRUE or FALSE. Example of general case of if statement is
If condition then
If condition is TRUE then sequence statements 1 is executed else sequence statement 2 is executed. With state machine, different actions are executed depending on the state hence different sequential statements used for different states. The reserved word ‘when’ is therefore important to specifying the states correctly. Example;
when state is S1 If condition then Sequential_statements1
This means that the machine will execute sequential statement 1 if condition is true, else sequential statement 2 is executed. This only happens when the state of the machine is S1.
The current state of the machine is stored in a state memory comprising a set of n flip flops.. It therefore follows that a machine will have 2n distinct states (Charles and John, 2018).
The general structure of a Mealy machine is shown below.
450253326032OutputOutput110379020336Next state LogicNext state Logic275153926032Flip Flops (state memory) Clock InputFlip Flops (state memory) Clock Input Input
Figure SEQ Figure \* ARABIC 1 Block diagram of a Mealy machine
Flip flops (all connected to a common clock signal) change state at each tick of the clock. The next state and the output functions is used to determine the behaviour of the circuit in discussion. To determine next state, the behaviour of flip flops is analysed. At rising edge of clock signal, each flip flop samples its input and transfers this value to the output depending on the characteristic equation of the flip-flop which is determined by the type of flip flop.
Characteristic equations express the next value of state variables as a function of current state and input. These equations are also called transition equations. For each of current state and input value, transition equations predict next state. These characteristic equations will change depending on the type of flip flop to be used for the design. For the D flip flop, the next output is latched directly from the input.
The proposed input sequence that will activate unlock is 0110111 and the state machine will accept an input X, and give two outputs, UNLK and HINT. The UNLK output should be 1 if and only if a 0 is received to the input X and the sequence of inputs received to X at the preceding seven clock ticks was 0110111. The HINT output should be 1 if and only if the current value of X is the correct one to move the machine closer to being in the “unlocked” state (with UNLK=1). The UNLK output depends on both the history of inputs into X and X’s current value while the HINT depends on both the state and the current X (indeed, if the current value at X produces HINT=0, then the clued-in user will want to change X before the clock tick).
A state and output table for the combination lock (state machine) is presented in the table below labelled Table 1.
S*, UNLK HINT
Table SEQ Table \* ARABIC 1:State and output table
2 Design of the state machine.
Table 1 shows the transition in states with respect to changes in input. The changes in states with the correct input sequence bring the lock closer to unlock with every ticking of the clock. The combinational lock has eight states namely A, B, C, D, E, F, G and H, two outputs UNLK and HINT and a single input X.
In the initial state, A, we assume that we have received no inputs in the required sequence; or rather the lock has been reset and we are looking for the first 0 in the sequence. Therefore, if we get 1 at the input, state A stagnates, and we move to state B when we receive a 0. In state B, we are looking for a 1. If we get it, we move on to C; if we do not, we can stay in B, since the 0 we just received might still turn out to be the first 0 in the required sequence. In each successive state, we move on to the next state if we get the correct input, and we go back to A or B if we get the wrong one. ...
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