Computer Architecture (Essay Sample)

COMPUTER ARCHITECTURE.
A) Give key features that distinguish:
RAM.
It means Random Access Memory. It is a form of computer storage that is used to store data being worked on. It is volatile. It looses it contents in the case of a power loss. It can be read into and read from.
ROM
Read-only memory (ROM) is a type of non-volatile memory used in computers and other electronic devices. Data stored in ROM can only be modified slowly, with difficulty, or not at all, so it is mainly used to store firmware for example programs. It is only read from and hard to write into. It is non- volatile, it does not loose its contents in the case of a power loss. It is used to store frequently used data and instruction.
PROM
This means Programmable Read Only Memory. It is a type of ROM that is initially blank but can written into by the use of special devices.
EPROM
Erasable Programmable Read Only Memory. It is initially blank but can be written into by the use of special devices. It can be erased and data written into.
EEPROM
EEPROM stands for Electrically Erasable Programmable Read Only Memory. It is initially blank but can be written into or changed by the help of electrical devices. Therefore it is easy to modify.
B) Discuss level 0-6 RAID technology
RAID
Redundant Arrays of Independent Disks
Three Common (mostly) Characteristics
RAID is a set of physical disk drives viewed by the operating system as a single logical drive.
Data are distributed across the physical drives of an array.
Redundant disk capacity is used to store parity information, which guarantees data recoverability in case of a disk failure.* * Except for RAID level 0.
Level 0 (Non-redundant)
Not a true member of RAID – no redundancy!
Data is striped across all the disks in the array
Each disk is divided into strips which may be blocks, sectors, or some other
convenient unit.
Strips from a file are mapped round-robin to each array member
A set of logically consecutive strips that maps exactly one strip to each array member
is a stripe
If a single I/O request consists of multiple contiguous strips, up to n strips can be handled in parallel, greatly reducing I/O transfer time.
Level 1 (Mirrored)
Only level where redundancy is achieved by simply duplicating all the data
Data striping is used as in RAID 0, but each logical strip is mapped to two separate physical disks
A read request can be serviced by disk with minimal seek and latency time
Write requests require updating 2 disks, but both can be updated in parallel, so no penalty
When a drive fails, data may be accessed from other drive
High cost for high performance
Usually used only for highly critical data.
Best performance when requests are mostly reads
Level 2 (Redundancy through Hamming Code)
Uses parallel access – all member disks participate in every I/O request
Uses small strips, often as small as a single byte or word
An error-correcting code (usually Hamming) is calculated across corresponding bits on each data disk, and the bits of the code are stored in the corresponding bit positions on multiple parity disks.
Useful in an environment where a lot of disk errors are expected
Usually expensive overkill.
Disks are so reliable that this is never implemented
Level 3 (Bit-Interleaved Parity)
Uses parallel access – all member disks participate in every I/O request
Uses small strips, often as small as a single byte or word
Uses only a single parity disk, no matter how large the disk array
A simple parity bit is calculated and stored
In the event of a failure in one disk, the data on that disk can be reconstructed from
the data on the others
Until the bad disk is replaced, data can still be accessed (at a performance penalty) in
reduced mode
Level 4 (Block-Level Parity)
Uses an independent access technique
each member disk operates independently, so separate I/O requests can be satisfied
in parallel.
More suitable for apps that require high I/O request rates rather than high data
transfer rates.
Relatively large strips
Has a write penalty for small writes, but not for larger ones (because parity can be calculated from values on other strips)
In any case, every write involves the parity disk
Level 5 (Block-Level Distributed Parity)
Like Level 4, but distributes parity strips across all disks, removing the parity bottleneck
Level 6 (Dual Redundancy)
Like Level 6, but provides 2 parity strips for each stripe, allowing recovery from 2
simultaneous disk failures.
C ) By use of a diagrams differentiate Traditional Hierarchical Bus Architecture from High performance Hierarchical Bus Architecture
Traditional Hierarchical Bus Architecture Example
High-performance Hierarchical Bus Architecture
Traditional hierarchical bus breaks down as higher and higher performance is seen in
the I/O devices
Incorporates a high-speed bus
specifically designed to support high-capacity I/O devices
brings high-demand devices into closer integration with the processor and at
the same time is independent of the processor
Changes in processor architecture do not affect the high-speed bus, and vice-
Versa
Sometimes known as a mezzanine architecture
High-performance Hierarchical Bus Architecture Example
D ) Explain the 5-stage pipelining in Intel 80486 Pipelining
Fetch - instructions are pre fetched into 1 of 2 16-byte pre fetch buffers.
Buffers are filled as soon as old data is consumed by instruction decoder
Instructions are variable length (1-11 bytes)
On average, about 5 instructions are fetched with each 16-byte load
Independent of rest of pipeline
Decode Stage 1
Op code and addressing mode info is decoded
This info always occurs in first 3 bytes of instruction
Decode Stage 2
Expands each op code into control signals for the ALU
Computation of more complex addressing modes
Execute
ALU operations
cache access
register update
Write Back
Write Back
May not be needed
Updates registers and status flags modified during Execute stage
If current instruction updates memory, the computed value is sent to the cache and to the bus-interface write buffers at the same time
E) Explain the architecture behind the I/O module.
Input-output interface provides a method for transferring information between internal storage and external I/O devices. Peripherals connected to a computer need special communication links for interfacing them with the central processing unit. The purpose of the communication link is to resolve the differences that exist between the central computer and each peripheral.
The major differences are:
  Peripherals are electro- mechanical and electromagnetic devices and their manner of
operation is different from the operation of the CPU and memory, which are electronic devices, therefore, a conversion of signal values may be required.
2.  The data transfer rate of peripherals is usually slower than the transfer rate of the CPU, and consequent