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Engineering
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Lab Report
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Topic:

Electronics (Simulation questions). Engineering Lab Report (Lab Report Sample)

Instructions:

The sample was a question and answer regarding the simulation of analogue and digital circuits.

source..
Content:

INTRODUCTION
Complementary Metal Oxide Semiconductor (CMOS), Transistor-Transistor Logic (TTL) and N-type metal-oxide-semiconductors (NMOS), are logic gates that are not only classified by their logical functions, but their families. It is therefore important to understand their characteristics and what they are capable of performing if we are to have a deeper understanding of logic gates. CMOS technology is usually used in the construction of integrated circuits (ICs) and also functions in digital logic circuits, microcontrollers, static RAM and microprocessors. They have a lower static power consumption and immune to noise CITATION ELP18 \l 1033 [1]. TTL this one as the name suggests, it constructed using a bipolar junction transistor, it does amplify functions as well as logic functions, they are widely used in computers, instruments, consumer electronics among other uses CITATION Ere03 \l 1033 [2]. NMOS uses the n-type field-effect transistors (MOSFETS) to implement the logic gates operation in digital circuits. They work by having an inversion layer at the p-type transistor, this is what is called the n-channel CITATION Sav05 \l 1033 [3]. This experiment seeks to give an ideal and practical understanding of these circuits when used as inverters.
SIMULATION RESULTS
Number #1
Figure SEQ Figure \* ARABIC 1: The inverter circuits of CMOS, TTL and NMOS
CMOS is simulated as below
Figure SEQ Figure \* ARABIC 2: Wave-form showing CMOS simulation
TTL simulation is as follows
NMOS is simulated as follows
Number #2
CMOS rise time, when the low-level voltage Vlow = 69.17372nV and the amplitude at this time is 5 – 69.17372 X 10-9 V= 5V
Rise time is the time it takes for the output signal to increase from 0.5 to 4.5V which is 10% and 90% of the volts respectively. Which is 3.429nS and fall time is 2.807nS
Rise and fall time for TTL; this occurs when the voltage is 8.290mV, so the amplitude shall be 5 – 8.290mV = 4.992V, whose 10% and 90% are 0.499V and 4.493V. which finally means that the rise time and fall time shall be:
8.290mV + 0.499V = 0.507V; 8.290 + 4.493V = 4.501V. So, the rise and fall times for TTL is 71.684nS and 1.973nS respectively.
For NMOS, the low voltage; Vlow = 1.371V
Amplitude shall be 3.488V-1.371V=2.117V. 10% and 90% of this shall be 0.212V and 1.905V respectively.
1.371 + 0.212 = 1.583V
1.371 + 1.905V = 3.276V
Therefore, the rise and fall time shall be 4.988nS and 3.933nS.
Number #3
Figure SEQ Figure \* ARABIC 3: The DC transfer characteristics
Number #4
Figure SEQ Figure \* ARABIC 4: CIrcuit showing the NMOS NAND gate
Figure SEQ Figure \* ARABIC 5:Simulation for NMOS NAND gate circuit
High voltage of 5V and a low voltage of 276.742nV. To calculate the voltage levels:
Voltage Vlow = 276.742nV and the amplitude at this time is 5 – 276.742 X 10-9 V= 5V.
We take the 10% and 90% we have 0.5V and 4.5V respectively.
Rise and fall times 4.195nS and 3.310nS respectively.
Number #5
Set NAND 1

Reset NAND 2

Output NAND 1

...
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